magnus919_agent-skills/fpga-development/templates/target-contract.md

FPGA target contract

Identity

• Board / revision:
• FPGA ordering code / package / speed grade:
• Evidence links (schematic, pinout, datasheet):
• Configuration transport and mode:
• Toolchain, exact versions, license requirements:
• HDL dialect / top module / source revision:

Clocks and reset

Clock	Source evidence	Frequency	Domain	Generated by	Relationship

• Reset source, polarity, assertion and release:
• PLL/MMCM lock dependency:
• Unknowns and artifact needed to resolve each:

I/O contract

Port	Direction	Pin/bank	I/O standard	Polarity	External load	Evidence

Decision and gate

• Decision:
• Risks:
• Programming/recovery path:
• No-programming conditions:
• Reviewer/date:

Completion instructions

Use UNKNOWN for absent evidence and name the artifact that resolves it. A board photo may support label identity but not pin mapping. A USB VID/PID may support the bridge family but not FPGA configuration mode. The reviewer should reject the contract when a missing value could cause electrical damage, an invalid constraint, or an unrecoverable programming action.

Example decision

HOLD: oscillator frequency is printed as 12 MHz but no schematic or datasheet confirms tolerance or pin. Request the board schematic and device clock input limits before creating timing constraints.