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* feat(electronics): add design and bench methodology * fix(electronics): retain compact diagnostic evidence * test(electronics): accept equivalent loading diagnostics
68 lines
3.6 KiB
Markdown
68 lines
3.6 KiB
Markdown
# Assembly and verification
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Acceptance is a chain from physical workmanship to observed behavior.
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## Unpowered inspection
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Inspect orientation, reference designators, solder bridges, wetting, lifted
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pads, connector seating, strain relief, and selectable pull-ups/address links.
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Check intended continuity and rail-to-rail/signal shorts with power removed;
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discharge capacitors first. Compare the assembly against the current BOM,
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schematic, layout, and assembly revision. Photograph or annotate anomalies.
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## Controlled first power
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Use a current-limited source when appropriate. Start with loads disabled and
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measure rail voltage, startup/steady current, reset behavior, and temperature.
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Add peripherals and outputs one at a time. Verify idle levels before enabling
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drivers. A current limit is a protective aid, not a replacement for a supply
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budget or fault analysis.
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## Functional acceptance
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Require an identity-level check for each bus device, a known input/output
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response, and documented reset and power-cycle behavior. For I2C, retain the
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raw capture or transaction log, address convention, measured rise time,
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effective pull-up, and recovery result. For analog or timed behavior, record
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calibration/reference, sample conditions, tolerance, and measurement setup.
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Repeat critical tests after mechanical handling and any relevant thermal or
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power condition. Record exact board/component/firmware revisions and every
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open risk. “It worked once” is not an acceptance criterion.
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| Failure at acceptance | Containment | Evidence needed before release |
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| Rail short or excess startup current | power off; isolate branch; inspect orientation/bridges | corrected inspection and current trace |
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| Correct rail, wrong idle state | disable load; check reset pulls and external straps | schematic-to-measured state comparison |
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| Bus responds but identity fails | stop application writes; preserve raw capture | documented identity read and address convention |
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| Intermittent after handling | repeat visual/continuity and capture under movement | reproducible mechanical condition or closure |
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| Recovery leaves line low | keep controller quiescent; reset/power-cycle holder | before/after line capture and owner |
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Release requires a named disposition for every failure: fixed and retested,
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accepted with an explicitly bounded risk, or blocked pending an artifact or
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measurement. A passing functional test cannot waive an unresolved electrical
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limit.
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The acceptance artifact is complete when another operator can reproduce the
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test, distinguish design evidence from instrument setup, and see the rollback
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or recovery path for every state-changing test.
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## Acceptance stage record
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At inspection, record component reference, defect class, image identifier, and
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disposition. At unpowered test, record meter mode, lead resistance, test points,
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and measured values; a continuity beep alone is insufficient. At first power,
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record current-limit setting, source voltage, startup peak, steady current,
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rail ripple, reset reason, and temperature. At functional test, record stimulus,
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expected response, actual response, repeat count, and environmental condition.
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For a soldered I2C connector, visual inspection may show correct pin placement,
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while end-to-end resistance proves only a low-current path. Far-end idle voltage,
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rise time with the actual probe, and identity readback establish separate facts.
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If those disagree, retain all results and localize the defect instead of marking
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the connector “passed.”
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Release is a disposition, not a checkbox: passed and repeatable, accepted with
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an explicitly bounded risk and owner, or blocked pending evidence. Rework must
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repeat the tests affected by the rework.
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