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* feat(electronics): add design and bench methodology * fix(electronics): retain compact diagnostic evidence * test(electronics): accept equivalent loading diagnostics
103 lines
5.2 KiB
Markdown
103 lines
5.2 KiB
Markdown
# I2C integration
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Treat I2C as an electrical bus plus a transaction contract.
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## Electrical budget
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Confirm every device's logic rail, open-drain behavior, input thresholds,
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leakage, sink current, clock-stretch support, and address straps. Calculate the
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effective parallel pull-up resistance, including module defaults. Choose `Rp`
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between the sink-current lower bound and rise-time upper bound:
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`Rp(min) = (VDD(max) - VOL(max)) / IOL(guaranteed)`
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Use the weakest guaranteed sink capability of every line driver at the
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required low voltage, not an absolute-maximum pin-current rating. Include rail
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and resistor tolerances; a buffer or rise-time accelerator changes the simple
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RC model and needs its own segment analysis.
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For the usual 30%-to-70% definition, `tr = 0.8473 × Rp × Cb`, so
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`Rp(max) = tr(max)/(0.8473 × Cb)`. TI's SLVA689 lists 1000/300/120 ns
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rise-time limits for Standard/Fast/Fm+ and 400/400/550 pF reference loads;
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the target datasheets and selected mode control. A smaller resistor improves
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rise time but increases low-level current and power. Measure actual rise time;
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do not treat a nominal resistor as proof of compliance.
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Source: TI SLVA689:
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https://www.ti.com/lit/an/slva689/slva689.pdf
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NXP UM10204 sections 3 and 7:
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https://www.nxp.com/docs/en/user-guide/UM10204.pdf
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### Worked design check
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Suppose the measured/estimated line capacitance is 120 pF, the rail is 3.3 V,
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and Fast-mode operation is required. The TI relation gives
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`Rp(max) ≈ 300 ns/(0.8473 × 120 pF) ≈ 2.95 kΩ`. If the device's low-level
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specification is 0.4 V at 3 mA, the simple lower bound is approximately
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`(3.3 - 0.4)/3 mA ≈ 967 Ω`. That interval still needs device-specific leakage,
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rail tolerance, parallel pull-ups, series resistors, and measured waveform
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checks. A 2.2 kΩ candidate may be reasonable for this stated case; it is not a
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portable default.
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If two 4.7 kΩ pull-ups are fitted on separate modules, their effective value is
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2.35 kΩ before any other pull-up is counted. Removing one may improve low-level
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current margin while preserving rise time. Conversely, replacing 4.7 kΩ with
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10 kΩ without measuring Cb can create a slow edge that a nominal frequency
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setting hides.
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## Bring-up and transaction evidence
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1. With power removed and stored energy discharged, check for unintended shorts.
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Then power the intended domains in their documented sequence and measure idle
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SDA/SCL levels. Do not apply pull-up power to an unpowered device unless its
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powered-off pin behavior permits it; protection structures may back-power it.
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2. At conservative speed, capture idle levels and one transaction. Record
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start/repeated-start/stop, 7-bit address, direction, ACK/NAK, register bytes,
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data, and clock stretching.
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3. Use a scan only as an address-response clue. Some probe methods can alter a
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device state; write-only devices may not respond to reads. A found address
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is not identity. Read a documented manufacturer/device/revision or status
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register before trusting the driver.
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4. Check reset state, register pointer semantics, endian/order, readiness delay,
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and documented repeated-start requirements.
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### Scan decision table
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| Scan result | Next test | Do not conclude |
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| Both lines low | isolate power/devices; identify holder | that the controller API is wrong |
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| Both lines high, no ACK | verify rail, reset, pins, straps, address notation | that the device is dead |
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| One or more ACKs | read documented identity/status register | that ACK proves device identity |
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| Unexpected extra ACK | remove modules one at a time; inspect parallel pull-ups/ghosts | that every responder is intended |
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| ACK then hang | capture phase and line owner; enforce timeout | that lower speed fixes root cause |
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Before a scan, decide whether the probing operation is read, write, or a
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controller-specific “quick” transaction, and whether the target permits it.
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Store that decision with the capture. For a write-capable device, a scan that
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touches a command register is a state mutation and needs an explicit rollback
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or reset plan.
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## Recovery ownership
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The controller owns timeout and recovery policy. Every wait for SCL, ACK, or a
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device-ready state has a deadline and reports the phase. If SDA is stuck low,
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NXP's bus-clear procedure calls for nine clock pulses; if it remains low, use
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hardware reset or power-cycle. If SCL is stuck low, reset or power-cycle first.
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Only pulse lines when the controller is electrically allowed to take ownership,
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all other controllers are quiescent, and the action cannot trigger an unsafe
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write. Capture line state before and after recovery and identify the holder if
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possible.
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## Fault localization
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If 0x48 ACKs but ADC identity/readback is wrong, capture address and direction,
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resolve 7-bit versus shifted 8-bit notation, then check identity register,
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pointer byte, repeated-start, reset readiness, and endian order. This localizes
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the fault to selection, transaction contract, reset, or bus corruption; it does
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not prove the library is at fault.
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If SDA is low before START, isolate modules and measure each branch. If it falls
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after a byte, capture ACK and ownership. If SCL is low, distinguish documented
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clock stretching from a stuck output using a deadline and waveform. Recovery
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records before/after state, pulse count, reset/power action, and line owner.
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