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* feat(electronics): add design and bench methodology * fix(electronics): retain compact diagnostic evidence * test(electronics): accept equivalent loading diagnostics
72 lines
3.5 KiB
Markdown
72 lines
3.5 KiB
Markdown
# Schematic to bench review
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Turn the design into a reviewable physical plan before applying power.
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## Review record
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For each net record:
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| Field | Required content |
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| Net and return | signal name, source, destination, explicit return path |
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| Pin identity | exact component reference, pin number, package/board revision |
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| State | power-off, reset, idle, active, fault level and polarity |
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| Limits | voltage, current, power, timing, absolute maximum and operating range |
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| Test point | probe/meter access, reference node, expected measurement |
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Read the exact schematic, board drawing, module documentation, and datasheet.
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The silkscreen or a familiar breakout is evidence of placement, not of pin
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function, voltage tolerance, pull-ups, or address straps. Mark every unknown.
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## Electrical reasoning
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Calculate each intentional load. For a resistor-fed LED, evaluate the range
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`I = (Vsupply - Vf) / R` across supply, forward-voltage, and resistor tolerance;
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then check the LED, resistor dissipation, and source/driver current limits. A
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GPIO is a control output, not a power supply. For an inductive load specify
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driver rating, flyback path, external supply, shared reference or isolation,
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and reset-time state. For analog inputs include source impedance, scaling,
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fault voltage, ADC range, reference/calibration, and filter corner.
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For mixed voltages, identify direction and topology. A bidirectional open-drain
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bus needs a translator that preserves release/high-impedance behavior; a
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push-pull signal may need a different level shifter. Do not infer tolerance from
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the board's supply label.
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## First-power gate
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With power removed, inspect orientation, rails, bridges, connector keying, and
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unpopulated options. Check intended continuity and absence of rail-to-rail or
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rail-to-signal shorts. Define a current limit and a stop condition before
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powering. Apply power with the load disabled where possible; measure rail
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voltage and current, reset state, and temperature. Add one signal group or
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peripheral at a time.
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The review is complete when a second engineer can wire or probe from the record,
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every numeric choice has a source or calculation, and unresolved facts are
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visible rather than hidden in assumptions.
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Sources: component datasheet and board schematic are controlling sources.
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For I2C electrical constraints use NXP UM10204 sections 3 and 7:
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https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/nxp-designs/931/1/UM10204.pdf
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## Worked review and stage gates
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For a 3.3 V GPIO driving an LED through 680 ohms, record GPIO4 → resistor →
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anode, cathode → ground, active-high, reset-off, and the LED datasheet's Vf
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range. At Vf=2.0 V, nominal current is `(3.3-2.0)/680 = 1.9 mA`; recalculate
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the extremes, resistor power (`I²R`), and GPIO limits. A continuity beep does
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not prove this load calculation, reset state, or driver safety.
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| Gate | Required evidence | Stop condition |
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| documentation | exact schematic/BOM/board/component revisions | pin, rail, polarity unknown |
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| unpowered | visual, continuity, rail-short record | unexpected conductive path |
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| first power | current limit, rail/current/reset/temperature | rail collapse or excess current |
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| signal | defined idle/active test-point readings | unexplained level or polarity |
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| integration | identity/readback and bounded timeout | scan-only or hanging driver |
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| release | reset/power-cycle and acceptance record | open electrical limit |
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Do not treat success at one gate as evidence for the next: a stable rail does
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not prove correct signaling, and a functional demo does not prove recovery.
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