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Magnus HedemarkandGitHub
f605e807f3
* feat(fpga-development): add design and verification methodology * feat(fpga-development): integrate electronics verification routing
32 lines
1.0 KiB
Systemverilog
32 lines
1.0 KiB
Systemverilog
module rv_buffer #(parameter integer DATA_WIDTH = 8) (
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input wire clk,
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input wire rst,
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input wire in_valid,
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output wire in_ready,
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input wire [DATA_WIDTH-1:0] in_data,
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output wire out_valid,
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input wire out_ready,
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output wire [DATA_WIDTH-1:0] out_data
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);
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reg full;
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reg [DATA_WIDTH-1:0] data_reg;
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assign in_ready = ~full | out_ready;
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assign out_valid = full;
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assign out_data = data_reg;
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always @(posedge clk) begin
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if (rst) begin
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full <= 1'b0;
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data_reg <= {DATA_WIDTH{1'b0}};
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end else begin
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case ({in_valid && in_ready, out_valid && out_ready})
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2'b10: begin full <= 1'b1; data_reg <= in_data; end
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2'b01: begin full <= 1'b0; end
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2'b11: begin full <= 1'b1; data_reg <= in_data; end
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default: begin end
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endcase
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end
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end
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endmodule
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