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* feat(fpga-development): add design and verification methodology * feat(fpga-development): integrate electronics verification routing
45 lines
1.5 KiB
Markdown
45 lines
1.5 KiB
Markdown
# Self-checking simulation plan
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## Provenance
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- DUT/top and source revision:
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- Simulator/version/command:
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- Defines, packages, libraries:
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- Seed policy:
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- Retained log/waveform paths:
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## Stimulus matrix
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| Case | Stimulus | Expected invariant/result | Evidence |
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|---|---|---|---|
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| reset at start | | | |
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| boundary values | | | |
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| illegal input | | | |
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| stall/backpressure | | | |
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| reset during traffic | | | |
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## Checks
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- Immediate/concurrent assertions:
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- Reference model:
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- Acceptance-count, ordering, payload-stability, occupancy, and reset-epoch invariants:
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- First-failure diagnostic fields:
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- Required nonzero exit behavior:
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- Negative control: injected defect and expected failure:
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## Coverage and conclusion
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- Coverage types and denominator:
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- Exclusions with rationale:
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- Uncovered behavior:
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- Result: PASS / FAIL / INCONCLUSIVE
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- Why the result does or does not establish synthesis or hardware behavior:
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## Review instructions
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The checker must be capable of failing independently of the DUT’s internal signals. Include at least one boundary case and one stalled or reset-interrupted case. Run a seeded mutation and retain its failing log. Record coverage exclusions with a reason tied to the contract; never use a percentage as a substitute for missing properties.
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## Example decision
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`INCONCLUSIVE`: all directed tests pass, but the mutation that removes FIFO-full protection also passes. Add a producer-overrun test and an assertion before accepting the suite.
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